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Creating Device Templates from Layouts

This export capability of SYMMIC turns any layout of devices into a single device, with additional base or top layers as an option. Version 2.7.0 introduces a new capability to choose precisely which components are exported and which are not. This option is useful for creating flip chips, building templates from scratch by parts, and converting other layouts that superposition cannot solve into a device which can be solved.

If some or all of the heated components are not included on export, then the fine details (e.g. heated gate segments) of each device in the layout may be merged, but the total power input and heated area in the layout is always preserved. Which features are merged is specified by a tolerance value, which is the maximum spacing between flux boundary conditions to be merged (on a given device template in the layout). Any vias or other components in the common layers may be retained if desired.

This capability has several uses, the first of which is to allow the modeling of large components, such as a Transmit/Receive (T/R) Module or even a Line Replaceable Unit (LRU). This provides the capability to calculate realistic boundary conditions for every device in a large component, as described in the following Boundary Conditions section, and in the example in the Top-Down Analysis chapter. A summary of the requirements and limitations of the export feature is given at the end of this section.

To export the layout, select Create device template... from the File menu. The “Create Device Template From Layout” dialog box will come up, as shown below.

All the various fields in the dialog will be populated with the values stored in the layout template (saved from the last time export was done). If the command-line version of SYMMIC (xSYMMIC) is run, then these defaults are the options that are used.

In the Save as field, enter the name of the device file to be written, or select the “...” button to browse for a file (to overwrite). In the second field enter a title for the exported device. If appended layers on the top or bottom are desired, then either type or navigate to the name of the template to get the layers from, and select the top or bottom. Otherwise set the number of layers to append to zero. As already mentioned above, the Smallest BC feature to retain (-1 for all) value determines whether flux boundary conditions will be merged together or not. A setting of “-1” will make no changes, and a setting of “0” will just remove the X and Y features that are no longer needed, if any exist (due to deleted components).

The Choose Components to Include button brings up a second dialog, as shown below.

This dialog lists all of the components in each device template in the layout which are not shared (i.e. belongsToMMIC=”true”), including components (e.g. vias) in the shared layers. The columns list the device number (as shown on the display in SYMMIC's main window), the component's name, the layer it is on, and what kind of boundary condition (BC) it has.

When this dialog is opened, the check boxes have a default setting according to the “toExport” flag for each of the components, which was set by SYMMIC on the previous export to “1” or “-1” to signify if that component was included or not, respectively. So in the example image above, all of the components in the device templates have toExport=”-1” since on the previous export none of them were included. The user should individually select or unselect the components as desired, then click OK to save these selections and return to the first dialog. If the users knows that the default selections are appropriate, then there is no need to enter this dialog. This is essentially what occurs when xSYMMIC is run for export (/e).

If a component containing a BC is unselected (not included on export), then the BC is handled as follows. If the BC is a BFLUX or on a top face, then it is retained and applied to the top-most retained component(s) underneath its original location, and a BFLUX is converted to an SFLUX. All other BCs in this situation are deleted.

Note that differences in the components included and the mesh resolution between the exported template and the original layout may result in different temperature results.

Exporting a Simplified Model

Before examining the case of appended layers, consider the example of the Generic FET Template (FET.xml) with default settings, placed in a layout by itself, and without mirroring. Clear all of the components (i.e. don't include any components that are not shared) and set the smallest BC tolerance to 100, then export it with zero attached layers. The resulting device and its solution mesh are as shown below. (See Chapter 5 for a full description of the Generic FET Template.) All of the upper component layers are gone, as well as the vias, and heat flux is the average over the total area occupied by the gate segments of the fully-refined FET. As a result, all of the parameters describing those layers are gone. The parameters still available are the bottom film boundary condition and a percent total power in the Heat Generation menu, as well as the Materials and Components specifications for the exported layers. There are several new parameters in the Mesh menu: Mesh Bias and Smallest Element Size, in addition to the normal Mesh Refinement parameter. The Smallest Element Size sets the X and Y element size in the heat generation areas, and Mesh Bias sets the rate at which the mesh size grows away from these areas. SYMMIC sets reasonable defaults for these parameters on export, but situations could arise – such as a layout of many exported devices – where the Smallest Element Size may need to be increased to keep the solution time reasonable.

Exported generic FET device is simplified but has the same total power dissipation.

In the simplified exported device, depending on the smallest resolve feature size, the heat may be generated by an average heat flux over a much larger area than in the fully-refined device layout (though the perimeter is unchanged). Therefore, the maximum temperature in the exported device may be significantly lower than in the fully-resolved device(s). In this case the exported device temperatures near the substrate surface are not representative. However, since both the substrate and the shim spread the heat as it travels downward, the temperature (and heat flux) distribution on the bottom of the exported device is identical to that of the fully-resolved device, and hence is useful for boundary condition calculations and subsystem analyses.

The ability to append additional layers is useful for exporting a component to the next subsystem level: for example, MMIC export to the T/R Module level, and T/R Module export to the LRU level. On export, the number of layers specified (by Append lower n layers from in the dialog box) are extracted from the given device template file and added to the bottom of the new device. When a file is selected, the available layers are shown in the dialog to aid selection. Only shared (common) layers are shown and available for appending. The expectation is that simple “device type” template files will be created for each subsystem level, (e.g. one for T/R Modules and one for LRUs). These need only have one component per layer, as well as the boundary conditions. On export the appended layers include the materials, layer thicknesses, and boundary conditions from the type file.

The “Create Device Template From Layout” dialog image above has a T/R Module device type file specified, containing two shared layers. The first layer, “Module1”, is the attachment of the module to whatever is beneath it (e.g. the LRU), and in this case it is an Indium solder. The second layer, “Module2”, is the heat spreader or shim that the MMIC above it attaches to, and it is composed of a Copper-Molybdenum-Copper laminate material.

Besides the layer thicknesses and materials, the device type file supplies boundary conditions for the exported device. This is examined in more detail in the Top-Down Analysis chapter, where the boundary conditions in a device type file for an LRU are changed.

Below is an example of the 2-Stage X-band Amp described in the MMIC Thermal Analysis section after being exported with the T/R Module layers shown above. On the left is a list of the new parameters that came with the appended layers. The Back/Front/Right/Left Module Offsets are the distances that the appended (module) layers extend on each side past the exported device. Since two layers were appended, there are two thickness parameters as well, Appended Layer 1/2 Thickness. In the components list dialog on the right the new Module Shim and Module Attach components can be seen. (Occasionally there will be a name conflict, especially after repeated exports, in which case component names may be prefixed by one or more letter-number pairs.)

Exported devices can be grouped into layouts just like any other device. For example, the T/R Module layout built in the Top-Down Analysis chapter is shown below. It is a layout of five different MMICs which were all exported with the same two module layers attached.

Template Creation by Parts

A second use of export is to create custom templates by assembling partial template “parts” in a layout, which when exported, becomes a stand-alone, valid template. This capability is especially useful for situations where none of the templates available accurately represent the entire device, but portions of the device are modeled by existing templates.

As an example, consider an array of FETs, where two FETs are close together and share the center pad. In addition, the outer pads have vias but the center one does not. Using an existing FET template, partial template “parts” can be created. These are “partial” templates because they do not have borders. Shown below are the three parts needed for this custom template.

On the left is the FET cell, in the center view is a half (center) pad without a via, and on the right is the pad with the via (not visible).

To create the custom FET, simply lay out the parts as shown below (via-pad, mirrored cell, pad (180°), pad, mirrored cell, and via-pad (180°)), making sure that all are touching each other.

Finally, simply export the layout (retaining all components and features) to create the stand-alone template. The resulting template is shown below as a sliced view, to see the vias.

When creating custom templates this way, the normal layout rules apply, but not those for superposition, as is always the case for export. Parts templates should use the same common layer definitions, and the new custom template will not retain any geometric parameters. Be sure to check the BCs on the new template.

Solving a Flip Chip Using Export

A third use of export is for layouts with boundary conditions that are unsuitable for superposition analysis (which is the way that SYMMIC solves layouts). One common example is a flip chip, where the heat sink boundary condition is on the top of the solder bumps in the layout instead of underneath the chip. For devices of this type, the layout can contain devices representing solder bumps, which simply contain the common layers, a solder bump and a (“extractable”) boundary condition on top of the bump. In turn, the powered device templates should not contain any cooling or heat sink boundary condition at all. As noted in Creating Valid Layout Models, this is not a valid layout to solve. However, export will assemble all of the devices and boundary conditions into a single device template which is valid and can be solved.

The recommended procedure for solving flip chips and calculating their thermal network is as follows.

1. Create a template for each of the devices needed for the chip layout.

   1. If many small “sub-devices” form a cell and only one network resistance is desired for that cell, then use export to create a simplified cell device from a layout of that cell (unless this cell must be flipped over to solve; see note under 5a below).

   2. If there is a boundary condition on the common layers that isn't appropriate for the chip once it is flipped (like a film or constant temperature on the bottom), remove it.

2. Create a template for the solder bumps or posts, that will connect the chip to the circuit board or other (module) layer, on which the boundary condition will be applied.

   1. All bumps or posts will need to be the same height to connect to the layer above, so either use the same parameter for each or fix their heights.

   2. The appended layer will attach to the top of the layer with the greatest zmax. If more than one layer shares this zmax, then all but one will be deleted and substituted with the chosen layer. Warning: Do not allow multiple layers to have the same zmax value if their zmin values differ.

   3. All bumps or posts which should attach to the top layer need to use the same layer (the zmax layer just defined). If they don't, then the components attached to the removed layers will be reattached to the retained layer during export.

   4. Keep in mind that the resistance for any solder-bump layer will be calculated by using the unweighted average of the temperatures in the center of each of the layer's components. So results will be improved if all of the solder bumps or posts contribute more-or-less equally to the heat flux transport to the boundary condition.

   5. If solder bumps directly on top of the devices connect to the appended layer, then place bumps on top of all the devices that connect to this layer, but make the imaginary bumps out of air. This creates a consistent thermal path for every device.

3. Now create a layout for the flip chip, using the templates from items 1 and 2 above.

4. Export this layout using the Export everything option. Select a type device file and append one or more layers to the top. This type device should include a boundary condition on the bottom. Note that when appending on top the type device is flipped upside down, so the bottom boundary condition is placed on the top face.

5. This exported template can be solved as normal, with one exception noted below. If an equivalent thermal impedance network is desired, then select the appropriate check box (Solve > Configure run > RC calculations...) before running the simulation.

   1. The exception is for a template with bumps on top of the devices, as noted in 2(e) above. In this case, it is necessary to first flip the template upside down before solving it*. This is easy to do in the device template editor: File > Edit device template..., then select Edit > Flip Upside Down. Save this new template (File > Apply then quit to exit the editor, then File > Save device(s)) and solve as normal.

*The reason for flipping the exported device template over before solution in this case is due to an assumption made by the equivalent thermal impedance algorithm, which is that the first impedance node is below each device's hottest spot and on top of the first common layer reached. If this is not true in the upright orientation, then the device template must be flipped over before solving.

Note that once a template is flipped upside down SYMMIC will not be able to perform the operation Solve > Boundary conditions > Extract at exports on it.

Export Requirements and Limitations

A summary of the requirements and limitations for the creation of device templates by the “export” of layouts is as follows.

1. Only layouts can be exported. A single device can be exported by first putting it in a layout (with Length and Width of the layout set to zero, so all of the device dimensions will be retained). In order to be valid for export, a layout must satisfy the following conditions:

   1. Each template must have the same number of common layers (i.e. "belongsToMMIC" layers), in sequential order, with a minimum of one.

   2. The same common layer in each template must have the same Zmin and Zmax.

   3. Every common layer must contain at least one common component.

2. The dimensions X, Y and Z of all the exported geometry is fixed after export. This does not apply to any appended layers. This means that all parameters and use tests that determined the geometry of each template is not present in the exported template. If the geometry needs to be changed, the user should go back to the layout, make the changes and export again.

3. The output mesh resolution is linked to a Smallest Element Size parameter and a bias. SYMMIC attempts to choose reasonable defaults, but it is the user's responsibility to ensure that the mesh size used is appropriate for the simulation. There is also an Appended Layers Mesh Size parameter that governs the mesh count in the thickness (Z) direction for the newly-appended layers, and its default setting is equal to the thinnest layer.

4. The components and layers which are retained and exported are chosen by the user, with one exception. All components that have belongsToMMIC=”true” are exported automatically. The choices that a user makes in the “Choose Components To Include” dialog are saved to the device template files in the “toExport” flag (if the user chooses to save the device template changes when prompted), and thereby become the default settings for the next time that a layout containing that device template is exported, or when xSYMMIC is run for exporting.

5. BCs marked with toExport < 0 will not be exported. Each layout used for export should have one and only one BC denoted as “extractable” (but it can be a shared BC (belongsToMMIC=”true”) present in every template), and it must be either a FILM or a CONSTANT BC on a top or bottom face.

6. Parameters are retained or created for each BC. SFLUX and BFLUX BCs on the exported geometry are fixed, with a global parameter (P1) on their percent power.

7. Layouts must remain within the X and Y limits of ±21 cm (210,000 microns) or errors may occur on export. Precision on export is 0.01 micron.

8. The SFLUX and BFLUX BCs for each device are flagged with a device number (dn) on export. The numbering starts at 1, and proceeds in the order of the device listing in the layout dialog.

9. If a component containing a BC is not included on export, then the BC is handled as follows.

   1. If the BC is a BFLUX or on a top face, then it is retained and applied to the top-most retained component(s) underneath its original location. The BFLUX is converted to an SFLUX. Avoid the case where several BCs are stacked vertically and all need to drop down to a single surface. Overlapped BCs are merged if possible, and otherwise deleted.

   2. All other BCs are deleted.

10. Layers can be appended on the top or the bottom, but if they are to be appended on top, then the following applies.

    1. The appended layer will attach to the top of the layer with the greatest zmax. If more than one layer shares this zmax, then all but one will be deleted and substituted with the chosen layer. Warning: do not allow multiple layers to have the same zmax value if their zmin values differ!

    2. All components which should attach to the top layer need to use the same layer (the zmax layer just defined). If they don't, then on export everything the components attached to the removed layers will be reattached to the retained layer.

11. The X and Y mesh is completely recalculated, but the Z mesh is maintained. The original mesh size parameters are replaced with three global parameters: Smallest Element Size, Mesh Bias in X and Y, and Z-Mesh Refinement. The user is encouraged to check the default values for the mesh resolution since they may need adjustment. The mesh can be checked by using Solve > Model check > Show mesh.

    1. The “Create Device Template From Layout” dialog has a parameter labeled Smallest BC feature to retain (-1 for all). If left at “-1” the selected components will be exported without any changes. If set to “0” then any features which are no longer needed (due to deleted components) will be removed, but no smoothing will occur. Finally, if set to a positive value, then both the unneeded features will be removed and any flux BCs which are closer together than the value set will be merged together. If export is being used to model a large subsystem, then deleting most or all of the components and smoothing the BCs is recommended. See the Use of Export to Model a T/R Module and LRU for a detailed example.

12. If a flip-chip is being created to find its equivalent thermal impedance network, then keep in mind that the resistance for any solder-bump layer will be calculated by using the unweighted average of the temperatures in the center of each of the layer's components. (See Exporting Layouts in chapter 4 for more information about creating flip chips.)

13. All layers having the same Zmin and Zmax values are joined together, even if they don't "belongToMMIC". This allows templates to be built up "by parts" and have non-common components (such as metal layers) connected.