CapeSym

Table of Contents

The g-Family Templates

The g-family templates provide a consistent set of device models for a generic high-electron mobility transistor (HEMT) process. All of the templates use the same stack-up for the package, substrate, and epi-layers, so they can be easily used together in a MMIC layout. The layers and materials are configured as GaN-on-Silicon for demonstration. These templates are designed to be modified through parameters which appear in the user interface under the Device menu. Additionally, devices may be combined in a layout and then exported to create a new type of device, but with a loss of parameters and decrease in mesh efficiency¹.

Common Layers

The following layers are common to all g-family devices and fill the common areas of the MMIC layout. Assuming a typical hetero-epitaxial growth structure [1], the epilayers begin with a nucleation layer, followed by a buffer layer to provide a lattice transition to the channel layer. The channel layer is followed by an active barrier layer. To keep the structure simple, the gate stem is placed directly on the barrier and completely surrounded by a passivation layer. Away from the active region, the passivation layer lies on top of the channel layer, and extends to cover the entire MMIC.

Adhesive. The solder, epoxy or other adhesive attaching the shim to the board or cold plate

Metal Shim. The metal shim, pedestal, or package slug to which the MMIC is attached

Solder. The solder or adhesive attaching the chip to the metal shim

Back Plating. The metal plating on the backside (bottom) of the substrate

Substrate. The wafer material, e.g. high-resistivity silicon for a GaN-on-Si process

Nucleation. The interface between substrate and the upper epi-layers

Buffer. The middle epi-layer of the device

Channel. The high electron mobility region (quasi-2D electron gas) forms at the top this active layer

Passivation. The layer of insulation over the channel.

Additional topside layers differ between devices. These device-specific layers are described in the separate help files associated with individual device templates. For simplicity, all device layers use a common set of parameter names within the templates. There are a total of 14 layers over all g-family device templates with thicknesses specified by the parameters T01 through T14. However, the descriptive names of these parameters are changed to refer to the main role of the layer in the active region of the device.

Materials

The g-family device templates contain a common set of materials. These basic materials are generic examples which have not been configured to any particular foundary process. For accurate results, foundary-specific materials should be added through the user interface or imported from existing templates. The basic materials (and their data sources) are listed in the Appendices of the users manual.

Application to Power Amplifier MMIC

A hypothetical power amplifier design was created from the g-family templates to demonstrate how the individual templates can be configured and combined to setup a large thermal analysis problem. As shown in the figure below, the amplifier consists of two stages. The first stage contains four instances of the gHEMT.xml template, configured to have 8-gates and dissipate 2 W per HEMT when the device is mirrored in the layout. Finger width was set at 120 microns, which gives power dissipation of 2/(8x0.120) ≈ 2.1 W per mm of gate periphery. In the gHEMT template, the sources are connected to through-substrate vias at the ends of the device by a source bridge filled with silicon dioxide. Vias were plated with gold, but assumed to be largely filled with air for the purposes of this thermal analysis.

Power amplifier created from the g-family templates. v = vias, c = capacitors, r = resistors.

The second stage contains four instances of the gHEMTarray.xml configured as double 8x120 HEMTs connected by a central via. Since each HEMT in the array template has 16 gates, the template was modified to reduce the number of gates. To do this, first the parameter Number of FETs was set to 2, and then 56 feature points in the x-direction were deleted using the Device Template Editor. This removed half of the gates from the middle of the first16-gate HEMT. The modified device (gHEMTarray_80x120.xml) was then mirrored in the layout to give the configuration shown below. There is a source bridge that connects the sources to all three vias. Vias were plated with gold but filled with air, as shown.

Cross-section through one of the four second stage HEMT arrays.

Heat dissipation in the each of the four devices in the second stage was set at 4 W, again equivalent to about 2.1 W per mm of gate periphery. So the first stage dissipated 8 W, while the second stage dissipated 16 W in total. To demonstrate that capacitor and resistor heating may be included in MMIC thermal analysis, each of these devices in the layout was configured to dissipate a nominal 0.1 W. There were 34 capacitors and resistors in the layout, adding 3.4 W to the dissipated power. The total power dissipated was 27.4 W.

The area of the MMIC was 4.4 x 4.8 mm. For the purposes of this analysis, the area for heat flow through the bottom of the package was considered to be the same as the MMIC area. When the package shim is larger than the die, the model should be adjusted to take this into account because the cross-sectional area of heat flow is a significant contributor to the peak temperature! The backside boundary condition at the bottom of all the layers was set at 300 Kelvin (K).

With this model in hand, we are now well-prepared to answer questions about the thermal performance of the amplifier. First question, do the interconnects at the surface have any effect on the distribution of temperatures in the HEMTs? The answer will determine whether it is necessary to include this level of detail for MMIC thermal analysis. A second question is the degree to which the resistors and capacitors need to be included in the thermal analysis, since 87.5% of power dissipation involves HEMT self-heating. One final question is whether the superposition thermal analysis performed by SYMMIC on a layout is as accurate as full simulation of the entire MMIC as a single mesh.

The entire layout was exported to a device template by way of the Create device template... command from the File menu. The resulting device model is depicted below. All of the interconnects, pads, vias, resistors, capacitors, HEMTs, and boundary conditions are now incorporated in one large mesh and so everything will be part of a single solve for all of the unknown temperatures. The alternative method of doing multiple solves on the active devices in the layout and combining them using superposition, does not include any effects of passive devices. The separate interconnects, pads and vias are all removed from the analysis of each active device and therefore fail to affect the final temperatures in the superposition analysis.

Power amplifier device after exporting the layout.

The full mesh for the exported amplifier contained over 270 million nodes where temperatures were to be calculated. So simulation of the exported amplifier required use of an iterative, preconditioned conjugate gradient (PCG) solver to reduce memory consumption. Even the task of meshing the amplifier required too much memory for a regular laptop or desktop computer. Cloudformation in Amazon Web Services (AWS) was used to launch a virtual private cluster of eight cloud instances based on the xSYMMIC in the Cloud product. Each instance had 758 GB of RAM to support meshing and solving such a large problem. The exported template was uploaded to the cluster using the Remote Run dialog, and solved for steady-state using xSYMMIC's built-in PCG solver via the command:

$ mpiexec -n 64 -ppn 8 -hostfile ipaddresses xSYMMIC gHEMT_PA_layout_export.xml

Meshing took about 46 seconds and produced an extremely large problem with 270,438,161 unique nodes. To optimize the solution of these 270 million simultaneous equations using a cluster of 64 concurrent processors, xSYMMIC first partitions the problem into approximately equal parts. Partitioning took about 311 seconds. This was followed by PCG linear solving and five additional non-linear iterations, for a total runtime of 46.5 minutes. The solution file was 16 GB and took more than 45 minutes to download from the cloud back to the desktop. The peak temperature calculated at the gates of the middle HEMTs in the second stage was 393.44 K.

Solution of exported power amplifier with 270 million temperature points.

This solution is so big that it could only be opened on a computer with at least 64 gigabytes (GB) of RAM. SYMMIC consumed 50.8 GB of RAM to load and graphically display the solution image shown above.

The layout could be solved faster on the desktop using superposition and the PARDISO direct solver. In this scenario there is no point in including passive devices in the superposition calculation since they would not contribute to the final temperatures anyway. So all passive devices (via, pad, and connector device templates) were removed from the layout prior to thermal analysis to speed up computation. Only devices actively dissipating power were included, as shown in the following figure. Note that the vias in the HEMTs remained in the calculations, as these were part of the HEMT device templates. Any thermal effects of these vias on the gate temperatures are included in the results.

Power amplifier layout with passive devices removed before superposition.

The superposition simulation with only active devices could be performed on an ordinary desktop having only four physical cores and 32 GB of RAM. This simulation took 46.5 minutes and consumed less than 10 GB of RAM at peak memory usage (when solving for the contribution of each second stage HEMT.) Temperatures were computed at 5,412,288 locations and the resulting solution file was about 320 megabytes. This solution is shown in the following figure.

SYMMIC provides a summary of the temperatures on each named component on each device in a layout. These component temperatures may be used to make a more detailed comparison between the solution obtained by simulating all devices as one huge mesh versus using superposition to solve only the active devices. The next figure compares the component temperatures associated with one of the middle HEMT arrays in the second stage of the amplifier for these two cases, and finds no important differences.

So we now have the answer to the first question. The interconnects at the surface DO NOT HAVE ANY EFFECT on the distribution of temperatures in the HEMTs. The peak temperature of 393.49 K was practically the same as that of 393.44 K in the full simulation. Heat spreading from the gate regions of the transistors through the epi-layers and substrate was much more significant than heat propagation along the thin interconnects at the surface. Therefore, it will not be necessary in the future to add the interconnects to the thermal analysis of any power amplifier with this type of layout.

Solution of power amplifier layout with passive devices removed.

Turning to the second question, the layout was further modified by removing all of the resistors and capacitors, reducing the total power dissipation to 24W.

Power amplifier layout with only the HEMT devices included.

Superpostion solution of the layout with only the HEMT devices included.

The superposition thermal analysis was repeated with just the HEMTs present, as shown above. Simulation time was reduced further to less than 22 minutes on the desktop. The peak temperature in the second stage HEMTs was 392.78 K, within half of a degree of the peak temperature for the full simulation. Again we find that HEMT self-heating is the dominate thermal effect. When resistors and capacitors are spread out across the MMIC and are dissipating relatively little power, they can usually be ignored during thermal analysis. For a more compact layout with more power dissipation in resistors or capacitors, it might be a good idea to include them in the initial thermal analysis to check that the heating effects are small before excluding them.

To answer the final question definitively, the HEMT-only analysis was repeated after exporting the layout to create a single mesh. This mesh contained 17,987,738 nodes and so required a lot less memory than the export of the full layout with all active and passive devices included. But the problem was still too big to solve on a desktop with only 32 GB of RAM. Consequently, the Remote Run dialog was again used to upload the simulation to a single instance running in AWS. This instance had 32 physical cores and 256 GB of RAM, so the problem could be solved directly using PARDISO at a cost of about $1.25 per hour. The entire cloud simulation took just 19 minutes and produced the solution shown below.

Direct solution of the exported MMIC with only the HEMT devices included.

With SYMMIC, solving a layout by superposition produces the same results as solving a full mesh of the entire MMIC. Furthermore, it is only necessary to include the transistors in the simulation, all other top-side details may be ignored for the purpose of thermal analysis. For the HEMT-only layout, the superposition analysis showed that the peak temperature at the gates of the second stage HEMTs would reach 392.78 K, while the full mesh analysis made a nearly identical prediction of 392.84 K. Moreover, the superposition analysis reduced the memory requirements and allowed the simulation to be performed on the desktop without recourse to additional cloud or cluster computing resources.

A detailed comparison of the component temperatures for one of the second stage devices was done for these simulations with only the HEMTs included. For every depth, from the gates down to the shim attachment layer, the temperatures are completely consistent between the superposition solution computed on the layout and the direct solution computed on the exported device, as shown in the following figure.

References

[1] T. Boles (2018) GaN-on-Silicon -- Present capabilities and future directions. AIP Conf. Proc. 1934. (http://doi.org/10.1063/1.5024484).