| CapeSym | |
Table of Contents |
The compact 2-stage X-band power amplifier described by Klockenhoff et al [1] will be used to demonstrate thermal analysis of a MMIC with multiple FETs. This GaN-on-SiC MMIC is about 2.5 × 3.8 mm. The driver stage consists of a single FET of 12x125µm gate length, while the power stage consists of two FETs each with 24 × 125µm gate length. The MMIC is capable of delivering 16W of output power at 8GHz in a very small chip area with power-added efficiency of about 30%.
Figure 1. Two-stage X-band power amplifier PA0202B.
Thermal analysis of this amplifier with SYMMIC involves the following easy steps:
1. Configure a template for each device where power is dissipated
2. Create a layout to define MMIC dimensions and set device locations
3. Set dissipated power levels and run the simulation
The first step in building a model of the MMIC, is to reconfigure the Generic FET Template to resemble the GaN-on-SiC driver stage transistor. Open the FET.xml template using the File menu Open... command, then access the Components... list from the Device menu and make the following changes to materials. Change the material for Substrate to SiC. Fill-in the source pad vias by changing the materials of Source Pad Via Hole and Source Pad Via Metal to SiC also. The source pads will be largely eliminated in the final model, so the source pad vias are filled with SiC, but the source vias are retained without changing their materials. Change the materials of Epi-layer 2, and Epi-layer 3 to GaN. The bottom epi-layer will represent the nucleation layer of AlN between SiC and GaN, so change Epi-layer 1 material to AlN. It may be helpful to take a slice through the center of the model to observe that the materials are correctly changed (Figure 2).
To create a FET similar to the actual device, make the following changes to the parameters:
|
Finger Width = 125 µm |
Source Pad Length = 5 µm |
|
Gate to Drain Distance = 2.1 µm |
Gate Bus Width = 20 µm |
|
Gate Length = 0.4 µm |
Drain Bus Width = 20 µm |
|
Gate to Source Distance = 1 µm |
Epi-Layer 1 Thickness = 0.1 µm |
|
Source Lengths = 49 µm |
Epi-Layer 2 Thickness = 2.3 µm |
|
Drain Lengths = 49 µm |
Epi-Layer 3 Thickness = 0.027 µm |
To model the 12-gate driver FET, set the Number of Gates to 6. (Only half the number of gates are modeled because the device is symmetric about a line through the center of the middle source.) The configured FET should now resemble Figure 2. Save the new device using Save device as... from the File menu. Give the new device the File name: “Stage1FET.xml” and Template title: “Stage 1 FET”.
Figure
2. The driver stage FET
model sliced through y-axis.
Figure
3. The Device Layout
Table dialog of Create layout...
Starting from the Stage 1 FET device, use Create layout... on the File menu to place the device in a MMIC. In the Device Layout Table set Title to “2-Stage X-band Amplifier”, Length = 3800 µm and Width = 2500 µm. To position the device on the MMIC, change X Position to 660 µm and Y Position to 750µm. To include the whole device, check the Mirror box. Finally, set Rotation to “90° Counterclockwise”. Click the OK button to update the display using the new parameters. Then save the layout using Save layout as... and give the file a descriptive name such as “XbandAmp.xml”.
The power stage FETs in this amplifier are similar to the driver stage FET, except there are twice as many gates in the same area. So open the Stage1FET.xml file by selecting Open... from the File menu, and change only the following parameters:
|
Drain Lengths = 24 µm |
|
Source Lengths = 24 µm |
|
Number of Gates = 12 |
The power stage FET should now resemble Figure 4. Save the new device using Save device as... from the File menu. Give the new device the File name: “Stage2FET.xml” and Template title: “Stage 2 FET”.
Figure
4. The power stage FET
device model.
Figure
5. Editing the Device
Layout Table to add the power stage FETs.
To add the power stage FETs to the MMIC, reopen the MMIC layout file (XbandAmp.xml) and use Edit layout... to access the Device Layout Table. Add new entries for the power stage by typing the name of the Stage 2 FET device file in the second and third entries of the table, as shown above (Figure 5). For the first Stage 2 FET set X Position = 2150 µm, Y Position = 220 µm, Rotation = “90° Counterclockwise”, and check the Mirror box. For the second Stage 2 FET, set X Position = 2150 µm, Y Position = 1310 µm, Rotation = “90° Counterclockwise”, and likewise check the Mirror box. Click the OK button to see the full amplifier model in the main window (Figure 6).
Finally, set the dissipated power on each of the FETs. Assuming the amplifier is being driven at full output power of 16W with a drain efficiency of about 37%, the power stage FETs dissipate about 4 W/mm while the driver stage FET dissipates 2 W/mm. Select the Stage 1 FET from the Device menu, and then access the Heat Generation... parameter list. Set the ON Power to 2 W/mm. Then Select each of the Stage 2 FETs in turn and set the ON Power to 4 W/mm. Assume that the heat sink attached to the backside of the MMIC maintains this surface at a constant 26.85°C, as defined by the default backside film parameters.
Figure
6.
The completed 2-stage X-band amplifier MMIC model.
Save the new power settings to the device template files by selecting Save device(s) from the File menu. (Devices 2 and 3 will save to the same file which is fine because they are identical.) Save the completed amplifier layout by clicking on Save layout from the File menu.
The power amplifier MMIC is now ready for thermal analysis. However, if the device layout is symmetric with respect to the MMIC boundaries, some simulation time can be saved by simplifying the layout to half of the full MMIC. To do this, edit the layout and make the following changes (Figure 7). Remove the second power stage FET by erasing the filename in the third Device Template File box. Only use half of the driver stage FET by unchecking the Mirror box. Set the Width of the MMIC to zero, which will cause the width to be set to the smallest value that contains all of the devices. Click the OK button to obtain a model of approximately half the MMIC.
Figure
7. Modifying the layout
to create a model of half the MMIC.
To simulate this model, select Run simulation... from the Solve menu. Simulation of the half MMIC model took less than 5 minutes on a Dell Precision T3600 Windows 7 workstation with an Intel Xeon E5-1260 running at 3.6 GHz having 4 cores with 32 Gb of shared RAM. The final solution contained temperatures at about 1.2 million nodes. Peak memory usage by the finite element direct solver was about 7.5 Gb.
Figure
8. Max. temperature plot
of the half MMIC model.
Figure 8 shows a plot of the hottest temperatures at each (x,y) position in the MMIC. The peak channel temperature of 206.5°C occurs in the middle of the power stage FETs. The effect of the driver stage FET is to elevate this peak channel temperature by only 6°C, as can be observed by repeating the simulation with only the power stage amplifier dissipating power. When the driver stage FET is simulated alone, its peak channel temperature is 66°C, but in the half device simulation the peak is at 101°C. So the temperature of the driver is significantly raised by the heat spreading from the power stage FETs.
It turns out that the FETs are not centered in the MMIC, so there is a certain amount of error in the half model analysis. To determine the magnitude of this error, simulation of the full MMIC (as shown in Figure 6) can be performed. Running this simulation does not require significantly more memory than the half-model MMIC because superposition of individual FETs is used to solve the MMIC. The final solution mesh contains about 2.5 million nodes, but the simulator decomposes the problem into independently solvable subproblems of less than 1.2 million nodes each. Since each of the three devices in the full MMIC model are individually simulated in two iterations, the total run time is increased to about 8.5 minutes.
The full MMIC simulation produces peak channel temperatures of 203.5°C and 202°C in the stage 2 FETs, and 100°C in the stage 1 FET. The power stage FET at the bottom (in Figure 1) has a slightly higher peak temperature than the one at the top, reflecting the real asymmetry of the MMIC. The full MMIC is not as hot as the half-model simulation because the backside surface area is under-represented in the half-model leading, incorrectly, to higher peak channel temperatures.
The following output, generated from a Snapshot... command in the Results menu, gives a summary of the temperatures in the solution, a listing of the parameter settings for all devices, and captures a screen shot of the main window display.
Snapshot of 2-stage X-band amplifier
Date: 4/25/2018 Time: 15:50:15
Template file: C:\TEMP\XbandAmp.xml
Entire layout covers X:[0,3800]µm Y:[0,2500]µm Z:[0,674.677]µm
Slice ranges are X:[-0.01,3800.01]µm Y:[-0.01,2500.01]µm Z:[-0.01,674.687]µm
Solution file: C:\TEMP\XbandAmp.rst
Entire solution covers X:[0,3800]µm Y:[0,2500]µm Z:[0,674.677]µm for time t=infinity (steady state)
Minimum temperature of 26.85 °C first found at x=0 µm, y=2500 µm, z=0 µm
Maximum
temperature of 203.514 °C first found at x=2342.5 µm,
y=652.35 µm, z=672.427 µm
From the Steady State Solution:
X location = [660,1045] µm
Y location = [750,1637] µm
Z location = [0,674.677] µm
|
Component |
Material |
Tmin (°C) |
Tmax (°C) |
Tavg (°C) |
|---|---|---|---|---|
|
Source Cap Metal |
Au |
69.9346 |
83.6959 |
77.5269 |
|
Drain Cap Metal |
Au |
72.8571 |
83.4305 |
77.7653 |
|
Gate Bus |
Au |
70.8823 |
88.6393 |
74.0018 |
|
Gates |
Au |
82.559 |
95.9335 |
92.2116 |
|
Drain Bus |
Au |
72.6896 |
79.5428 |
75.7421 |
|
Sources |
Au |
70.0453 |
85.5041 |
77.8862 |
|
Drains |
Au |
73.9196 |
84.7809 |
78.7066 |
|
Source Via in Epi-layer 3 |
Au |
71.627 |
80.6629 |
77.6432 |
|
Epi-layer 3 |
GaN |
70.0441 |
100.424 |
79.0172 |
|
Source Via in Epi-layer 2 |
Au |
71.5498 |
80.6616 |
77.629 |
|
Epi-layer 2 |
GaN |
69.9764 |
100.319 |
78.642 |
|
Source Via in Epi-layer 1 |
Au |
71.547 |
80.5801 |
77.6129 |
|
Epi-layer 1 |
AlN |
69.9751 |
83.9857 |
78.2657 |
|
Source Via Metal |
Au |
69.0908 |
80.5781 |
74.5905 |
|
Source Via Holes |
Air |
69.1019 |
80.544 |
74.4169 |
|
Substrate |
SiC |
65.4095 |
83.8629 |
71.6844 |
|
Solder |
Au80Sn20 |
64.8949 |
74.1091 |
69.9169 |
|
Metal Shim |
W80Cu20 |
60.2322 |
71.4401 |
65.3901 |
|
Backside Adhesive |
Epoxy |
26.85 |
64.1211 |
44.5442 |
|
Source Pad |
Au |
69.7371 |
71.4844 |
70.7154 |
|
Source Pad Via Metal |
SiC |
68.825 |
71.1719 |
69.824 |
|
Source Pad Via Hole |
SiC |
68.8641 |
71.0353 |
69.7971 |
Peak temperature for this device is 100.424°C.
|
Parameter |
Value |
|---|---|
|
Number of Gates (in half device) |
6 |
|
Source 7 Length |
49 microns |
|
Source 6 Length |
49 microns |
|
Source 5 Length |
49 microns |
|
Source 4 Length |
49 microns |
|
Source 3 Length |
49 microns |
|
Source 2 Length |
49 microns |
|
Source 1 Length |
49 microns |
|
Default Source Length |
49 microns |
|
Source Cap Length Offset |
2 microns |
|
Drain 7 Length |
49 microns |
|
Drain 6 Length |
49 microns |
|
Drain 5 Length |
49 microns |
|
Drain 4 Length |
49 microns |
|
Drain 3 Length |
49 microns |
|
Drain 2 Length |
49 microns |
|
Drain 1 Length |
49 microns |
|
Default Drain Length |
49 microns |
|
Drain Cap Length Offset |
2 microns |
|
Source Pad Via Length |
4.9 microns |
|
Source Pad Via Metal |
2 microns |
|
Source Pad Via Width |
50 microns |
|
Source Via Width |
70 microns |
|
Source Via Length |
15 microns |
|
Source Via Metal |
2 microns |
|
Gate T Metal |
0 (Off or On) |
|
Gate to Source Distance |
1 microns |
|
Gate Length |
0.4 microns |
|
Gate to Drain Distance |
2.1 microns |
|
Finger Width |
125 microns |
|
Source Pad to Boundary |
100 microns |
|
Source Pad Length |
5 microns |
|
Drain Bus to Boundary |
100 microns |
|
Drain Bus Width |
20 microns |
|
Drain Bus to Source |
10 microns |
|
Source Bridge |
0 (Off or On) |
|
Gate Bus to Source |
10 microns |
|
Gate Bus Width |
20 microns |
|
Gate Bus to Boundary |
100 microns |
|
Backside Adhesive Thickness |
50 microns |
|
Metal Shim Thickness |
500 microns |
|
Solder Thickness |
20 microns |
|
Substrate Thickness |
100 microns |
|
Epi-Layer 1 (bottom) Thickness |
0.1 microns |
|
Epi-Layer 2 (middle) Thickness |
2.3 microns |
|
Epi-Layer 3 (top) Thickness |
0.027 microns |
|
Ohmic Metal Thickness |
0.25 microns |
|
Gate Metal Thickness |
1 microns |
|
Drain Cap Metal Thickness |
1 microns |
|
Source Cap Metal Thickness |
2 microns |
|
Gate T Metal Thickness |
1 microns |
|
Source Bridge Metal Thickness |
2 microns |
|
Segment 4 Width |
0.5 microns |
|
Segment 3 Width |
0.5 microns |
|
Segment 2 Width |
0.5 microns |
|
Segment 1 Width |
0.125 microns |
|
Percent Power on Segment 4 |
0 percent |
|
Percent Power on Segment 3 |
0 percent |
|
Percent Power on Segment 2 |
90 percent |
|
Percent Power on Segment 1 |
10 percent |
|
Backside Film Temperature (K) |
300 Kelvin |
|
Backside Film Coefficient (W/um^2.K) |
1 W/um^2.K |
|
Cycle Start |
0 seconds |
|
OFF Duration |
5e-05 seconds |
|
OFF Power (W/mm) |
0 W/mm |
|
ON Duration |
2.5e-05 seconds |
|
ON Power (W/mm) |
2 W/mm |
|
Mesh Refinement |
1 scalar |
|
|
|
|
|
|
|
Solver Nonlinear Iterations |
On |
|
Relative Tolerance |
0.0001 |
|
Iterate Superposition |
On |
|
Pardiso Solver |
On |
|
Stefan-Boltzmann |
5.67e-20 |
X location = [2150,2535] µm
Y location = [220,1112] µm
Z location = [0,674.677] µm
|
Component |
Material |
Tmin (°C) |
Tmax (°C) |
Tavg (°C) |
|---|---|---|---|---|
|
Source Cap Metal |
Au |
107.247 |
158.739 |
139.527 |
|
Drain Cap Metal |
Au |
108.364 |
157.284 |
135.921 |
|
Gate Bus |
Au |
106.623 |
162.503 |
121.33 |
|
Gates |
Au |
135.719 |
190.579 |
174.372 |
|
Drain Bus |
Au |
107.661 |
137.76 |
122.977 |
|
Sources |
Au |
107.925 |
162.947 |
141.152 |
|
Drains |
Au |
117.091 |
160.517 |
142.272 |
|
Source Via in Epi-layer 3 |
Au |
111.658 |
155.623 |
143.277 |
|
Epi-layer 3 |
GaN |
107.913 |
203.514 |
144.733 |
|
Source Via in Epi-layer 2 |
Au |
111.237 |
155.607 |
143.108 |
|
Epi-layer 2 |
GaN |
107.352 |
203.191 |
142.742 |
|
Source Via in Epi-layer 1 |
Au |
111.219 |
154.645 |
142.919 |
|
Epi-layer 1 |
AlN |
107.339 |
158.985 |
140.785 |
|
Source Via Metal |
Au |
99.0715 |
154.616 |
124.242 |
|
Source Via Holes |
Air |
99.1114 |
154.504 |
123.238 |
|
Substrate |
SiC |
89.6278 |
158.648 |
109.005 |
|
Solder |
Au80Sn20 |
88.0375 |
117.929 |
101.672 |
|
Metal Shim |
W80Cu20 |
77.4425 |
106.461 |
87.0327 |
|
Backside Adhesive |
Epoxy |
26.85 |
80.3684 |
53.1902 |
|
Source Pad |
Au |
105.934 |
112.104 |
109.812 |
|
Source Pad Via Metal |
SiC |
98.8215 |
111.419 |
103.264 |
|
Source Pad Via Hole |
SiC |
98.8914 |
110.372 |
103.075 |
Peak temperature for this device is 203.514°C.
|
Parameter |
Value |
|---|---|
|
Number of Gates (in half device) |
12 |
|
Source 7 Length |
24 microns |
|
Source 6 Length |
24 microns |
|
Source 5 Length |
24 microns |
|
Source 4 Length |
24 microns |
|
Source 3 Length |
24 microns |
|
Source 2 Length |
24 microns |
|
Source 1 Length |
24 microns |
|
Default Source Length |
24 microns |
|
Source Cap Length Offset |
2 microns |
|
Drain 7 Length |
24 microns |
|
Drain 6 Length |
24 microns |
|
Drain 5 Length |
24 microns |
|
Drain 4 Length |
24 microns |
|
Drain 3 Length |
24 microns |
|
Drain 2 Length |
24 microns |
|
Drain 1 Length |
24 microns |
|
Default Drain Length |
24 microns |
|
Drain Cap Length Offset |
2 microns |
|
Source Pad Via Length |
4.9 microns |
|
Source Pad Via Metal |
2 microns |
|
Source Pad Via Width |
50 microns |
|
Source Via Width |
70 microns |
|
Source Via Length |
15 microns |
|
Source Via Metal |
2 microns |
|
Gate T Metal |
0 (Off or On) |
|
Gate to Source Distance |
1 microns |
|
Gate Length |
0.4 microns |
|
Gate to Drain Distance |
2.1 microns |
|
Finger Width |
125 microns |
|
Source Pad to Boundary |
100 microns |
|
Source Pad Length |
5 microns |
|
Drain Bus to Boundary |
100 microns |
|
Drain Bus Width |
20 microns |
|
Drain Bus to Source |
10 microns |
|
Source Bridge |
0 (Off or On) |
|
Gate Bus to Source |
10 microns |
|
Gate Bus Width |
20 microns |
|
Gate Bus to Boundary |
100 microns |
|
Backside Adhesive Thickness |
50 microns |
|
Metal Shim Thickness |
500 microns |
|
Solder Thickness |
20 microns |
|
Substrate Thickness |
100 microns |
|
Epi-Layer 1 (bottom) Thickness |
0.1 microns |
|
Epi-Layer 2 (middle) Thickness |
2.3 microns |
|
Epi-Layer 3 (top) Thickness |
0.027 microns |
|
Ohmic Metal Thickness |
0.25 microns |
|
Gate Metal Thickness |
1 microns |
|
Drain Cap Metal Thickness |
1 microns |
|
Source Cap Metal Thickness |
2 microns |
|
Gate T Metal Thickness |
1 microns |
|
Source Bridge Metal Thickness |
2 microns |
|
Segment 4 Width |
0.5 microns |
|
Segment 3 Width |
0.5 microns |
|
Segment 2 Width |
0.5 microns |
|
Segment 1 Width |
0.125 microns |
|
Percent Power on Segment 4 |
0 percent |
|
Percent Power on Segment 3 |
0 percent |
|
Percent Power on Segment 2 |
90 percent |
|
Percent Power on Segment 1 |
10 percent |
|
Backside Film Temperature (K) |
300 Kelvin |
|
Backside Film Coefficient (W/um^2.K) |
1 W/um^2.K |
|
Cycle Start |
0 seconds |
|
OFF Duration |
5e-05 seconds |
|
OFF Power (W/mm) |
0 W/mm |
|
ON Duration |
2.5e-05 seconds |
|
ON Power (W/mm) |
4 W/mm |
|
Mesh Refinement |
1 scalar |
|
|
|
|
|
|
|
Solver Nonlinear Iterations |
On |
|
Relative Tolerance |
0.0001 |
|
Iterate Superposition |
On |
|
Pardiso Solver |
On |
|
Stefan-Boltzmann |
5.67e-20 |
X location = [2150,2535] µm
Y location = [1310,2202] µm
Z location = [0,674.677] µm
|
Component |
Material |
Tmin (°C) |
Tmax (°C) |
Tavg (°C) |
|---|---|---|---|---|
|
Source Cap Metal |
Au |
105.168 |
157.477 |
138.292 |
|
Drain Cap Metal |
Au |
106.408 |
156.099 |
134.703 |
|
Gate Bus |
Au |
104.651 |
161.238 |
120.162 |
|
Gates |
Au |
133.589 |
189.172 |
173.024 |
|
Drain Bus |
Au |
105.702 |
136.631 |
121.807 |
|
Sources |
Au |
105.849 |
161.668 |
139.915 |
|
Drains |
Au |
115.086 |
159.313 |
141.032 |
|
Source Via in Epi-layer 3 |
Au |
109.552 |
154.356 |
142.035 |
|
Epi-layer 3 |
GaN |
105.837 |
202.049 |
143.485 |
|
Source Via in Epi-layer 2 |
Au |
109.131 |
154.34 |
141.867 |
|
Epi-layer 2 |
GaN |
105.279 |
201.728 |
141.501 |
|
Source Via in Epi-layer 1 |
Au |
109.113 |
153.362 |
141.678 |
|
Epi-layer 1 |
AlN |
105.266 |
157.749 |
139.55 |
|
Source Via Metal |
Au |
97.0237 |
153.333 |
123.065 |
|
Source Via Holes |
Air |
97.0655 |
153.231 |
122.065 |
|
Substrate |
SiC |
87.2093 |
157.413 |
107.842 |
|
Solder |
Au80Sn20 |
85.6873 |
116.891 |
100.548 |
|
Metal Shim |
W80Cu20 |
75.5987 |
105.421 |
86.018 |
|
Backside Adhesive |
Epoxy |
26.85 |
79.7849 |
52.728 |
|
Source Pad |
Au |
103.855 |
111.781 |
108.6 |
|
Source Pad Via Metal |
SiC |
96.7651 |
111.096 |
102.069 |
|
Source Pad Via Hole |
SiC |
96.8373 |
110.062 |
101.88 |
Peak temperature for this device is 202.049°C.
|
Parameter |
Value |
|---|---|
|
Number of Gates (in half device) |
12 |
|
Source 7 Length |
24 microns |
|
Source 6 Length |
24 microns |
|
Source 5 Length |
24 microns |
|
Source 4 Length |
24 microns |
|
Source 3 Length |
24 microns |
|
Source 2 Length |
24 microns |
|
Source 1 Length |
24 microns |
|
Default Source Length |
24 microns |
|
Source Cap Length Offset |
2 microns |
|
Drain 7 Length |
24 microns |
|
Drain 6 Length |
24 microns |
|
Drain 5 Length |
24 microns |
|
Drain 4 Length |
24 microns |
|
Drain 3 Length |
24 microns |
|
Drain 2 Length |
24 microns |
|
Drain 1 Length |
24 microns |
|
Default Drain Length |
24 microns |
|
Drain Cap Length Offset |
2 microns |
|
Source Pad Via Length |
4.9 microns |
|
Source Pad Via Metal |
2 microns |
|
Source Pad Via Width |
50 microns |
|
Source Via Width |
70 microns |
|
Source Via Length |
15 microns |
|
Source Via Metal |
2 microns |
|
Gate T Metal |
0 (Off or On) |
|
Gate to Source Distance |
1 microns |
|
Gate Length |
0.4 microns |
|
Gate to Drain Distance |
2.1 microns |
|
Finger Width |
125 microns |
|
Source Pad to Boundary |
100 microns |
|
Source Pad Length |
5 microns |
|
Drain Bus to Boundary |
100 microns |
|
Drain Bus Width |
20 microns |
|
Drain Bus to Source |
10 microns |
|
Source Bridge |
0 (Off or On) |
|
Gate Bus to Source |
10 microns |
|
Gate Bus Width |
20 microns |
|
Gate Bus to Boundary |
100 microns |
|
Backside Adhesive Thickness |
50 microns |
|
Metal Shim Thickness |
500 microns |
|
Solder Thickness |
20 microns |
|
Substrate Thickness |
100 microns |
|
Epi-Layer 1 (bottom) Thickness |
0.1 microns |
|
Epi-Layer 2 (middle) Thickness |
2.3 microns |
|
Epi-Layer 3 (top) Thickness |
0.027 microns |
|
Ohmic Metal Thickness |
0.25 microns |
|
Gate Metal Thickness |
1 microns |
|
Drain Cap Metal Thickness |
1 microns |
|
Source Cap Metal Thickness |
2 microns |
|
Gate T Metal Thickness |
1 microns |
|
Source Bridge Metal Thickness |
2 microns |
|
Segment 4 Width |
0.5 microns |
|
Segment 3 Width |
0.5 microns |
|
Segment 2 Width |
0.5 microns |
|
Segment 1 Width |
0.125 microns |
|
Percent Power on Segment 4 |
0 percent |
|
Percent Power on Segment 3 |
0 percent |
|
Percent Power on Segment 2 |
90 percent |
|
Percent Power on Segment 1 |
10 percent |
|
Backside Film Temperature (K) |
300 Kelvin |
|
Backside Film Coefficient (W/um^2.K) |
1 W/um^2.K |
|
Cycle Start |
0 seconds |
|
OFF Duration |
5e-05 seconds |
|
OFF Power (W/mm) |
0 W/mm |
|
ON Duration |
2.5e-05 seconds |
|
ON Power (W/mm) |
4 W/mm |
|
Mesh Refinement |
1 scalar |
|
|
|
|
|
|
|
Solver Nonlinear Iterations |
On |
|
Relative Tolerance |
0.0001 |
|
Iterate Superposition |
On |
|
Pardiso Solver |
On |
|
Stefan-Boltzmann |
5.67e-20 |
The SYMMIC template-based thermal simulator allows high fidelity thermal analysis of a new MMIC design to be completed in half an hour using standard PC hardware. The total setup time for this example MMIC was about 20 minutes starting from a generic device template. Run time of the steady-state analysis of the full MMIC required a total runtime of only about 10 minutes on a 64-bit workstation.
[1] H. Klockenhoff, R. Behtash, J. Würfl, W. Heinrich, G. Tränkle, “A Compact 16 Watt X-Band GaN-MMIC Power Amplifier,” Microwave Symposium Digest, 2006 IEEE MTT-S International, pp. 1844-1849.
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